| 765 | 7 | 21 |
| 下载次数 | 被引频次 | 阅读次数 |
提出了一种采用现场可编程门阵列器件FPGA实现定点IIR低通数字滤波器的方案,该方案采用只读存储器ROM查找表的位串行分布式算法,极大地减少硬件电路的规模,提高了电路的执行速度。以一个四阶IIR低通数字滤波器电路的实现为例,说明了设计过程,对所设计的电路进行了验证。结果表明,电路工作正确可靠,满足了设计要求。
Abstract：A method to implement the IIR digital filters using FPGA is proposed. The bit - serial distributed a rithmetic based on the ROM look - up table is employed. A four - tap lowpass IIR filter is taken as an example. The realized circuit is simulated and the results show that the circuit works reliably and perfectly.
[1] 郭继昌,向晖,滕建辅,等．基于FPGA的FIR滤波器的 实现[J]．电子技术应用,2000,(5):60-62．
[2] Balsara P T, Harper D T. Understanding VLSI bit serial multipliers, Education[J]. IEEE Transactions on, 1996,39(2): 19-28.
[3] Hatirnaz I,Gurkaynak F K,Leblebici Y. A modular and scalable architecture for the realization of high - speed programmable rank order filters [A]. ASIC/SOC Conference [C]. 1999,382-386.
[4] Peled A,Liu B. A new hardware realization of digital filters [J]. IEEE Trans on Acoustics Speech and Signal Processing Newsletter, 1974, (6): 456-462.
基本信息:
DOI：
中图分类号:TN713;
引用信息:
[1]李香萍.基于FPGA的IIR低通数字滤波器的实现[J].天津工程师范学院学报,2005(03):46-49.
基金信息: